The following are the events and their indices. These are the default programming in the application data base and in the DLL data base. It also correlates to the result indices in the log file.
Each table consumes 120 entries and the unoccupied ones are different from Pentium to Pentium Pro tables.
Note that indices below are the indices defined by the tool and they do NOT necessarily match the ones described in the processor programmer reference manual .
Pentium Processor Events for Counter 0
Index |
Event |
Encoding |
0 | Data Read | 0x00 |
1 | Data Write | 0x01 |
2 | Data Read or Data Write | 0x28 |
3 | Data TLB Miss | 0x02 |
4 | Data Read Miss | 0x03 |
5 | Data Write Miss | 0x04 |
6 | Data Read or Data Write Miss | 0x29 |
7 | Write (hit) to M or E state lines | 0x05 |
8 | Data Cache Lines Written Back | 0x06 |
9 | External Snoops | 0x07 |
10 | External Data Cache Snoop Hits | 0x08 |
11 | Memory Accesses in Both Pipes | 0x09 |
12 | Bank Conflicts | 0x0a |
13 | Misaligned Data Memory or I/O References | 0x0b |
14 | Code Read | 0x0c |
15 | Code TLB Miss | 0x0d |
16 | Code Cache Miss | 0x0e |
17 | Any Segment Register Loaded | 0x0f |
18 | Branches | 0x12 |
19 | BTB Hits | 0x13 |
20 | Taken Branch or BTB Hit | 0x14 |
21 | Pipeline Flushes | 0x15 |
22 | Instructions Executed | 0x16 |
23 | Instructions Executed in the v-pipe e.g. parallelism | 0x17 |
24 | Locked Bus Cycle | 0x1c |
25 | I/O Read or Write Cycle | 0x1d |
26 | Non-cacheable memory reads | 0x1e |
27 | FLOPs | 0x22 |
28 | Breakpoint match on DR0 Register | 0x23 |
29 | Breakpoint match on DR1 Register | 0x24 |
30 | Breakpoint match on DR2 Register | 0x25 |
31 | Breakpoint match on DR3 Register | 0x26 |
32 | Hardware Interrupts | 0x27 |
33 | Clocks while a bus cycle is in progress (bus util.) | 0x18 |
34 | Number of clocks stalled due to full write buffers | 0x19 |
35 | Pipeline stalled waiting for data memory read | 0x1a |
36 | Stall on write to an E or M state line | 0x1b |
37 | Pipeline stalled due to addr generation interlock | 0x1f |
38 | Bus ownership latency | 0x2a |
39 | MMX instructions executed in U-pipe | 0x2b |
40 | Number of L1 M-state line sharing | 0x2c |
41 | EMMS instructions executed | 0x2d |
42 | Bus utilization due to processor activity | 0x2e |
43 | Saturated MMX instructions executed | 0x2f |
44 | Cycles not in HLT state | 0x30 |
Pentium Processor Events for Counter 0 (continued)
Index |
Event |
Encoding |
45 | MMX data memory reads | 0x31 |
46 | Floating point stalls | 0x32 |
47 | D1 starving but instruction FIFO empty | 0x33 |
48 | MMX data memory writes | 0x34 |
49 | Pipeline flushes due to wrong branch prediction | 0x35 |
50 | MMX misaligned data memory reference | 0x36 |
51 | Returns miss predictions | 0x37 |
52 | MMX Multiply interlock | 0x38 |
53 | Returns executed | 0x39 |
54 | BTB bogus entry detected | 0x3a |
55 | MMX writes backed - pipe stalled | 0x3b |
56 | Reserved | 0x3c |
57 | Reserved | 0x3d |
58 | Reserved | 0x3e |
59 | NULL event | 0x3f |
60 | Reserved | 0xFF |
61 | Reserved | 0xFF |
.... | ||
118 | Reserved | 0xFF |
119 | Reserved | 0xFF |
Pentium Processor Events for Counter 0
Index |
Event |
Encoding |
|
0 | Data Read | 0x00 | |
1 | Data Write | 0x01 | |
2 | Data Read or Data Write | 0x28 | |
3 | Data TLB Miss | 0x02 | |
4 | Data Read Miss | 0x03 | |
5 | Data Write Miss | 0x04 | |
6 | Data Read or Data Write Miss | 0x29 | |
7 | Write (hit) to M or E state lines | 0x05 | |
8 | Data Cache Lines Written Back | 0x06 | |
9 | External Snoops | 0x07 | |
10 | External Data Cache Snoop Hits | 0x08 | |
11 | Memory Accesses in Both Pipes | 0x09 | |
12 | Bank Conflicts | 0x0a | |
13 | Misaligned Data Memory or I/O References | 0x0b | |
14 | Code Read | 0x0c | |
15 | Code TLB Miss | 0x0d | |
16 | Code Cache Miss | 0x0e | |
17 | Any Segment Register Loaded | 0x0f | |
18 | Branches | 0x12 | |
19 | BTB Hits | 0x13 | |
20 | Taken Branch or BTB Hit | 0x14 | |
21 | Pipeline Flushes | 0x15 | |
22 | Instructions Executed | 0x16 | |
23 | Instructions Executed in the v-pipe e.g. parallelism | 0x17 | |
24 | Locked Bus Cycle | 0x1c | |
25 | I/O Read or Write Cycle | 0x1d | |
26 | Non-cacheable memory reads | 0x1e | |
27 | FLOPs | 0x22 | |
28 | Breakpoint match on DR0 Register | 0x23 |
Pentium Processor Events for Counter 0 (continued)
Index |
Event |
Encoding |
|
29 | Breakpoint match on DR1 Register | 0x24 | |
30 | Breakpoint match on DR2 Register | 0x25 | |
31 | Breakpoint match on DR3 Register | 0x26 | |
32 | Hardware Interrupts | 0x27 | |
33 | Clocks while a bus cycle is in progress (bus util.) | 0x18 | |
34 | Number of clocks stalled due to full write buffers | 0x19 | |
35 | Pipeline stalled waiting for data memory read | 0x1a | |
36 | Stall on write to an E or M state line | 0x1b | |
37 | Pipeline stalled due to addr generation interlock | 0x1f | |
38 | Bus ownership transfers | 0x2a | |
39 | MMX instructions executed in V-pipe | 0x2b | |
40 | Number of L1-line sharing | 0x2c | |
41 | MMX ---> FP transitions | 0x2d | |
42 | Writes to non-cacheable memory | 0x2e | |
43 | Saturated MMX operations executed | 0x2f | |
44 | Ex stage stalled due to a D-TLB miss | 0x30 | |
45 | MMX data read misses | 0x31 | |
46 | Taken branches | 0x32 | |
47 | D1 starving but only 1 inst in inst FIFO | 0x33 | |
48 | MMX data write misses | 0x34 | |
49 | Pipeline flushes-wrong branch prediction in WB-Stage | 0x35 | |
50 | MMX wait memory read - pipe stalled | 0x36 | |
51 | Returns predicted (correctly & uncorrectly) | 0x37 | |
52 | MMX store stall due to previous operation | 0x38 | |
53 | RSB overflows | 0x39 | |
54 | BTB miss-prediction or a not-taken branch | 0x3a | |
55 | Stall on MMX write to E or M line | 0x3b | |
56 | Reserved | 0x3c | |
57 | Reserved | 0x3d | |
... | |||
118 | Reserved | 0xFF | |
119 | Reserved | 0xFF |
Pentium Pro Processor Events
Index |
Encoding |
Umask |
Event |
0 | 0x43 | 0x00 | DCU - Data Mem Refs |
1 | 0x45 | 0x00 | DCU - Lines In |
2 | 0x46 | 0x00 | DCU - M Lines In |
3 | 0x47 | 0x00 | DCU - M Lines Out |
4 | 0x48 | 0x00 | DCU - Miss Outstanding |
5 | 0x80 | 0x00 | IFU - iFetch |
6 | 0x81 | 0x00 | IFU - iFetch Miss |
7 | 0x85 | 0x00 | IFU - ITLB Miss |
8 | 0x86 | 0x00 | IFU - Mem Stall |
9 | 0x87 | 0x00 | IFU - Inst Lrngth Decoder Stall |
L2 Cache | |||
10 | 0x28 | 0x0F | L2 Instructions Fetches [MESI] |
11 | 0x29 | 0x0F | L2 Data Loads [MESI] |
12 | 0x2A | 0x0F | L2 Data Stores [MESI] |
13 | 0x24 | 0x00 | Lines Allocated in L2 |
14 | 0x26 | 0x00 | Lines Removed from L2 |
15 | 0x25 | 0x00 | Modified Lines ALLOCATED in L2 |
16 | 0x27 | 0x00 | Modified Lines REMOVED from L2 |
Pentium Pro Processor Events (continued)
Index |
Encoding |
Umask |
Event |
17 | 0x2E | 0x0F | L2 Requests [MESI] |
18 | 0x21 | 0x00 | L2 Address Strobes |
19 | 0x22 | 0x00 | Cycles Data Bus was BUSY |
20 | 0x23 | 0x00 | Cycles Data Bus was BUSY in READ |
External Bus Logic (EBL)2 | |||
21 | 0x62 | 0x00 | DRDY is asserted [Self/Processor] |
22 | 0x62 | 0x20 | DRDY is asserted [Any/any agent] |
23 | 0x63 | 0x00 | LOCK is asserted [Self] |
24 | 0x63 | 0x20 | LOCK is asserted [Any ] |
25 | 0x60 | 0x00 | BUS requests outstanding |
26 | 0x65 | 0x00 | Burst Read transactions [Self] |
27 | 0x65 | 0x20 | Burst Read transactions [Any ] |
28 | 0x66 | 0x00 | Read for Ownership Transactions [Self] |
29 | 0x66 | 0x20 | Read for Ownership Transactions [Any ] |
30 | 0x67 | 0x00 | Write Back Transactions [Self] |
31 | 0x67 | 0x20 | Write Back Transactions [Any ] |
32 | 0x68 | 0x00 | Instruction FETCH Transactions [Self] |
33 | 0x68 | 0x20 | Instruction FETCH Transactions [Any ] |
34 | 0x69 | 0x00 | BUS Invalidate Transactions [Self] |
35 | 0x69 | 0x20 | BUS Invalidate Transactions [Any ] |
36 | 0x6A | 0x00 | BUS Partial Writes [Self] |
37 | 0x6A | 0x20 | BUS Partial Writes [Any ] |
38 | 0x6B | 0x00 | BUS Partial Transactions [Self] |
39 | 0x6B | 0x20 | BUS Partial Transactions [Any ] |
40 | 0x6C | 0x00 | BUS Trans IO [Self] |
41 | 0x6C | 0x20 | BUS Trans IO [Any ] |
42 | 0x6D | 0x00 | BUS DEFFERED Transactions [Self] |
43 | 0x6D | 0x20 | BUS DEFFERED Transactions [Any ] |
44 | 0x6E | 0x00 | BUS BURST Transactions [Self] |
45 | 0x6E | 0x20 | BUS BURST Transactions [Any ] |
46 | 0x70 | 0x00 | BUS- ALL transactions [Self] |
47 | 0x70 | 0x20 | BUS- ALL transactions [Any ] |
48 | 0x6F | 0x00 | BUS- Memory Transactions [Self] |
49 | 0x6F | 0x20 | BUS- Memory Transactions [Any ] |
50 | 0x64 | 0x00 | BUS- cycles processor RECEIVING DATA |
51 | 0x61 | 0x00 | BUS- Cycles processor driving BNR pin |
52 | 0x7A | 0x00 | BUS- Cycles processor driving HIT pin |
53 | 0x7B | 0x00 | BUS- Cycles processor driving HITM pin |
54 | 0x7E | 0x00 | BUS is SNOOP Stalled |
Floating Point Unit | |||
55 | 0xC1 | 0x00 | FP Ops RETIRED [Counter 0 Only] |
56 | 0x10 | 0x00 | FP Ops EXECUTED [Counter 0 Only] |
57 | 0x11 | 0x00 | FP Assist [Counter 1 Only] |
58 | 0x12 | 0x00 | FP MUL [Counter 1 Only] |
59 | 0x13 | 0x00 | FP DIV [Counter 1 Only] |
60 | 0x14 | 0x00 | FP Cycles Divider is Busy [Counter 0 Only] |
Memory Ordering | |||
61 | 0x03 | 0x00 | Mem Ord - LD Blocks |
62 | 0x04 | 0x00 | Mem Ord - SB Drains |
63 | 0x05 | 0x00 | Mem Ord - Misalign Mem Refs |
Instruction Decoding and Retirement | |||
64 | 0xC0 | 0x00 | INST - Instructions Retired |
65 | 0xC2 | 0x00 | INST - uOps Retired |
66 | 0xD0 | 0x00 | INST - Instructions decoded |
Interrupts | |||
67 | 0xC8 | 0x00 | INT - Hardware INTERRUPTS received |
68 | 0xC6 | 0x00 | INT - Cycles INterrupts are DISABLED |
Pentium Pro Processor Events (continued)
Index |
Encoding |
Umask |
Event |
69 | 0xC7 | 0x00 | INT - Cycles Ints are Pending But disabled |
Branches | |||
70 | 0xC4 | 0x00 | Branch Insts Retired |
71 | 0xC5 | 0x00 | BR Miss PRED Retired |
72 | 0xC9 | 0x00 | BR Taken Retired |
73 | 0xCA | 0x00 | BR Miss PRED Taken Retired |
74 | 0xE0 | 0x00 | BR Insts Decoded |
75 | 0xE2 | 0x00 | BRs That miss the BTB |
76 | 0xE4 | 0x00 | BR Bogus |
77 | 0xE6 | 0x00 | BACLEAR is asserted |
Stalls | |||
78 | 0xA2 | 0x00 | STALLS - Resource Stalls |
79 | 0xD2 | 0x00 | STALLS - Partial RAT Stalls |
Segment Register Loads | |||
80 | 0x06 | 0x00 | Segment Reg Loads |
Clocks | |||
81 | 0x79 | 0x00 | CPU CLK UnHalted |
82 | 0xFF | 0xFF | Reserved |
83 | 0xFF | 0xFF | Reserved |
84 | 0xFF | 0xFF | Reserved |
85 | 0xFF | 0xFF | Reserved |
86 | 0xFF | 0xFF | Reserved |
87 | 0xFF | 0xFF | Reserved |
88 | 0xFF | 0xFF | Reserved |
89 | 0xFF | 0xFF | Reserved |
90 | 0xFF | 0xFF | Reserved |
91 | 0xFF | 0xFF | Reserved |
92 | 0xFF | 0xFF | Reserved |
... | |||
118 | 0xFF | 0xFF | Reserved |
119 | 0xFF | 0xFF | Reserved |
Table of Contents